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1999 data sheet m pd3728 mos integrated circuit the m pd3728 is a high-speed and high sensitive color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the m pd3728 has 3 rows of 7300 pixels, and it is a 2-output/color type ccd sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels. therefore, it is suitable for 600 dpi/a3 high-speed color digital copiers and so on. features ? valid photocell : 7300 pixels 3 ? photocell's pitch : 10 m m ? line spacing : 40 m m (4 lines) red line-green line, green line-blue line ? color filter : primary colors (red, green and blue), pigment filter (with light resistance 10 7 lx?hour) ? resolution : 24 dot/mm (600 dpi) a3 (297 420 mm) size (shorter side) ? drive clock level : cmos output under 5 v operation ? data rate : 40 mhz max. (20 mhz/1 output) ? output type : 2 outputs in phase/color ? power supply : +12 v ? on-chip circuits : reset feed-through level clamp circuits voltage amplifiers ordering information part number package m pd3728d ccd linear image sensor 36-pin ceramic dip (600 mil) document no. s13878ej1v0ds00(1st edition) date published april 1999 n cp(k) printed in japan 7300 pixels 3 color ccd linear image sensor the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd3728 2 data sheet s13878ej1v0ds00 block diagram 8 13 14 5 3 1 36 34 32 30 29 23 28 16 24 22 21 15 clb 1l gnd 20 2 1 (blue) tg1 (blue) tg2 (green) tg3 (red) v out 2 (blue, even) v out 1 (blue, odd) v out 3 (green, odd) v out 4 (green, even) v out 6 (red, even) v out 5 (red, odd) 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7299 s7300 d129 d134 (green) photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7299 s7300 d129 d134 (red) photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7299 s7300 d129 d134 rb fff f f f f f f f f 6 4 2 35 33 31 gnd gnd gnd gnd gnd gnd 9 10 7 v od f
m pd3728 3 data sheet s13878ej1v0ds00 pin configuration (top view) ccd linear image sensor 36-pin ceramic dip (600 mil) ? m pd3728d photocell structure diagram photocell array structure diagram (line spacing) m 10 m m 7 m m m 3 channel stopper aluminum shield blue photocell array 10 m m green photocell array 10 m m red photocell array 10 m m 4 lines (40 m) m 4 lines (40 m) m red green blue 1 1 1 7300 7300 7300 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 v out 4 gnd v out 6 gnd v out 5 gnd v od rb 10 nc nc nc 1 2 tg3 gnd nc nc output signal 4 (green, even) ground output signal 6 (red, even) ground output signal 5 (red, odd) ground output drain voltage reset gate clock shift register clock 10 no connection no connection no connection shift register clock 1 shift register clock 2 transfer gate clock 3 (for red) ground no connection no connection output signal 3 (green, odd) ground output signal 1 (blue, odd) ground output signal 2 (blue, even) ground reset feed-through level clamp clock last stage shift register clock 1 shift register clock 20 no connection no connection no connection shift register clock 2 shift register clock 1 transfer gate clock 1 (for blue) transfer gate clock 2 (for green) no connection no connection v out 3 gnd v out 1 gnd v out 2 gnd clb 1l 20 nc nc nc 2 1 tg1 tg2 nc nc 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 f f f f f f f f f f f f
m pd3728 4 data sheet s13878ej1v0ds00 absolute maximum ratings (t a = +25 c) parameter symbol ratings unit output drain voltage v od C0.3 to +15 v shift register clock voltage v f 1 , v f 1l , v f 10 , v f 2 , v f 20 C0.3 to +15 v reset gate clock voltage v f rb C0.3 to +15 v reset feed-through level clamp clock voltage v f clb C0.3 to +15 v transfer gate clock voltage v f tg1 to v f tg3 C0.3 to +15 v operating ambient temperature t a C25 to +60 c storage temperature t stg C40 to +100 c caution exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. recommended operating conditions (t a = +25 c) parameter symbol min. typ. max. unit output drain voltage v od 11.4 12.0 12.6 v shift register clock high level v f 1h , v f 1lh , v f 10h , v f 2h , v f 20h 4.5 5.0 5.5 v shift register clock low level v f 1l , v f 1ll , v f 10l , v f 2l , v f 20l C0.3 0 +0.5 v reset gate clock high level v f rbh 4.5 5.0 5.5 v reset gate clock low level v f rbl C0.3 0 +0.5 v reset feed-through level clamp clock high level v f clbh 4.5 5.0 5.5 v reset feed-through level clamp clock low level v f clbl C0.3 0 +0.5 v transfer gate clock high level note v f tg1h to v f tg3h 4.5 v f 1h v f 1h v (v f 10h )(v f 10h ) transfer gate clock low level v f tg1l to v f tg3l C0.3 0 +0.5 v data rate 2f f rb C 2 40 mhz note when transfer gate clock high level (v f tg1h to v f tg3h ) is higher than shift register clock high level (v f 1h (v f 10h )), image lag can increase. remark pin 9 ( f 10) and pin 28 ( f 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 mhz or so.
m pd3728 5 data sheet s13878ej1v0ds00 electrical characteristics t a = +25 c, v od = 12 v, f f rb = 1 mhz, data rate = 2 mhz, storage time = 10 ms, light source: 3200 k halogen lamp +c-500s (infrared cut filter, t = 1mm), input signal clock = 5 v p-p parameter symbol test conditions min. typ. max. unit saturation voltage v sat 1.5 2.0 C v saturation exposure red ser 0.35 lx ? s green seg 0.39 lx ? s blue seb 0.31 lx ? s photo response non-uniformity prnu v out = 1 v 6 18 % average dark signal note 1 ads1 light shielding 1.0 5.0 mv ads2 0.5 5.0 mv dark signal non-uniformity note 1 dsnu1 light shielding 2.0 5.0 mv dsnu2 1.0 5.0 mv power consumption p w 600 800 mw output impedance z o 0.3 0.5 k w response red r r 3.9 5.6 7.3 v/lx ? s green r g 3.6 5.1 6.6 v/lx ? s blue r b 4.5 6.4 8.3 v/lx ? s image lag note 1 il1 v out = 1 v 2.0 5.0 % il2 1.0 5.0 % offset level note 2 v os 4.0 5.0 6.0 v output fall delay time note 3 t d v out = 1 v 20 ns register imbalance ri v out = 1 v 0 4.0 % total transfer efficiency tte v out = 1 v, 95 98 % data rate = 40 mhz response peak red 630 nm green 540 nm blue 460 nm dynamic range note 1 dr11 v sat /dsnu1 1000 times dr12 v sat /dsnu2 2000 times dr21 v sat / s bit1 2000 times dr22 v sat / s bit2 4000 times reset feed-through noise note 2 rftn light shielding C500 +200 +500 mv random noise note 1 s bit1 light shielding, bit clamp C 1.0 C mv s bit2 mode (t7 = 150 ns) C 0.5 C mv s line1 light shielding, line C 4.0 C mv s line2 clamp mode (t19 = 3 m s) C 2.0 C mv notes 1. ads1, dsnu1, il1, dr11, dr21, s bit1 and s line1 show the specification of v out 1 and v out 2. ads2, dsnu2, il2, dr12, dr22, s bit2 and s line2 show the specification of v out 3 to v out 6. 2. refer to timing chart 2, 5 . 3. when the fall time of f 1l (t2) is the typ. value (refer to timing chart 2, 5 ).
m pd3728 6 data sheet s13878ej1v0ds00 input pin capacitance (t a = +25 c, v od = 12 v) parameter symbol pin name pin no. min. typ. max. unit shift register clock pin capacitance 1 c f 1 f 1 13 350 500 pf 23 350 500 pf f 10 9 350 500 pf shift register clock pin capacitance 2 c f 2 f 2 14 350 500 pf 24 350 500 pf f 20 28 350 500 pf last stage shift register clock pin capacitance c f l f 1l 29 10 pf reset gate clock pin capacitance c f rb f rb 8 10 pf reset feed-through level clamp clock pin capacitance c f clb f clb 30 10 pf transfer gate clock pin capacitance c f tg f tg1 22 100 pf f tg2 21 100 pf f tg3 15 100 pf remark pins 13, 23 ( f 1) and pin 9 ( f 10) are connected each other inside of the device. pins 14, 24 ( f 2) and pin 28 ( f 20) are connected each other inside of the device.
m pd3728 7 data sheet s13878ej1v0ds00 timing chart 1 (bit clamp mode, for each color) note input the f rb and f clb pulses continuously during this period, too. 9 11 13 10 12 14 tg1 to 1 ( 10) 2 ( 20) rb clb v out 1, 3, 5 v out 2, 4, 6 tg3 1 3 5 7 15 17 19 21 23 25 2 4 6 8 16 18 20 22 24 26 optical black (96 pixels) invalid photocell (6 pixels) valid photocell (7300 pixels) invalid photocell (6 pixels) 28 30 120 122 27 29 119 121 123 125 127 129 124 126 128 130 131 132 7426 7428 7430 7432 7425 7427 7429 7431 7433 7435 7437 7434 7436 7438 1l note note f f f f f f f f f
m pd3728 8 data sheet s13878ej1v0ds00 timing chart 2 (bit clamp mode, for each color) symbol min. typ. max. unit t1, t2 0 50 ns t1, t2 0 5 ns t3 20 50 ns t4 5 200 C ns t5, t6 0 20 ns t7 20 150 ns t8, t9 0 20 ns t10 C10 note 1 +50 C ns t11 C5 note 2 +50 ns 90 % t10 t1' t5 t6 t4 t3 t2' t d v os rftn 10 % t11 t9 t8 t7 t1 t2 90 % 1 ( 10) 2 ( 20) 1l rb clb v out 1 to v out 6 10 % 90 % 10 % 10 % 90 % 10 % 90 % 10 % f f f f f f f
m pd3728 9 data sheet s13878ej1v0ds00 notes 1. min. of t10 shows that the f rb and f clb overlap each other. 2. min. of t11 shows that the f 1l and f clb overlap each other. rb clb 90 % 90 % t10 f f 1l clb 90 % 90 % t11 f f
m pd3728 10 data sheet s13878ej1v0ds00 timing chart 3 (bit clamp mode, for each color) symbol min. typ. max. unit t11 C5 note 2 +50 ns t12 3000 10000 ns t13, t14 0 50 ns t15, t16 900 1000 ns notes 1. input the f rb and f clb pulses continuously during this period, too. 2. min. of t11 shows that the f 1l and f clb overlap each other. 1l clb 90 % 90 % t11 f f tg1 to tg3 1 ( 10) 2 ( 20) 1l rb clb t12 t14 t13 90 % 10 % t15 90 % 90 % t11 90 % note 1 t16 f f f f f f f f f 1 ( 10) 2 ( 20) 2 v or more 2 v or more 2 ( 20) 1l 2 v or more 0.5 v or more f f f f f f f f 1 ( f 10), f 2 ( f 20) cross points f 1l, f 2 ( f 20) cross points remark adjust cross points ( f 1 ( f 10), f 2 ( f 20)) and ( f 1l, f 2 ( f 20)) with input resistance of each pin.
m pd3728 11 data sheet s13878ej1v0ds00 timing chart 4 (line clamp mode, for each color) note set the f rb to high level during this period. remark inverse pulse of the f tg1 to f tg3 can be used as f clb. 9 11 13 10 12 14 v out 1, 3, 5 v out 2, 4, 6 1 3 5 7 15 17 19 21 23 25 2 4 6 8 16 18 20 22 24 26 28 30 120 122 27 29 119 121 123 125 127 129 124 126 128 130 131 132 7426 7428 7430 7432 7425 7427 7429 7431 7433 7435 7437 7434 7436 7438 note note tg1 to tg3 1 ( 10) 2 ( 20) 1l rb clb f f f f f f f f f optical black (96 pixels) invalid photocell (6 pixels) valid photocell (7300 pixels) invalid photocell (6 pixels)
m pd3728 12 data sheet s13878ej1v0ds00 timing chart 5 (line clamp mode, for each color) symbol min. typ. max. unit t1, t2 0 50 ns t1, t2 0 5 ns t3 20 50 ns t4 5 200 C ns t5, t6 0 20 ns 1( 10) f 2( 20) ? t1' t5 t6 t4 t3 t2' t d v os rftn 10 % t1 t2 90 % 1l rb clb v out 1 to v out 6 10 % 90 % 10 % 90 % 10 % 90 % 10 % f ff f f f f f f
m pd3728 13 data sheet s13878ej1v0ds00 timing chart 6 (line clamp mode, for each color) symbol min. typ. max. unit t12 3000 10000 ns t13, t14 0 50 ns t15, t16 900 1000 ns t17, t18 100 1000 ns t19 200 t12 ns t20, t21 0 20 ns note set the f rb to high level during this period. remark inverse pulse of the f tg1 to f tg3 can be used as f clb. f 1 ( f 10), f 2 ( f 20) cross points f 1l, f 2 ( f 20) cross points remark adjust cross points ( f 1 ( f 10), f 2 ( f 20)) and ( f 1l, f 2 ( f 20)) with input resistance of each pin. 2 ( 20) 1 ( 10) 2 ( 20) 2 v or more 2 v or more f ff f f f f 1l 2 v or more 0.5 v or more tg1 to tg3 1 ( 10) 2 ( 20) 1l rb clb t12 note t14 t13 90 % 10 % 90 % 10 % t15 t20 t21 t18 t17 90 % 90 % t19 t16 f f f f f f f f f
m pd3728 14 data sheet s13878ej1v0ds00 definitions of characteristic items 1. saturation voltage: v sat output signal voltage at which the response linearity is lost. 2. saturation exposure: se product of intensity of illumination (i x ) and storage time (s) when saturation of output voltage occurs. 3. photo response non-uniformity: prnu the output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. this is calculated by the following formula. 4. average dark signal: ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. prnu (%) = x = x j : output voltage of valid pixel number j d x d x : maximum of ? x j - x ? x 7300 s j=1 7300 x j 100 ads (mv) = d j : dark signal of valid pixel number j 7300 s j=1 7300 d j x register dark dc level v out d x
m pd3728 15 data sheet s13878ej1v0ds00 5. dark signal non-uniformity: dsnu absolute maximum of the difference between ads and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula. 6. output impedance: z o impedance of the output pins viewed from outside. 7. response: r output voltage divided by exposure (ix ? s). note that the response varies with a light source (spectral characteristic). 8. image lag: il the rate between the last output voltage and the next one after read out the data of a line. v 1 il (%) = 100 v out d j : dark signal of valid pixel number j dsnu (mv) : maximum of ? d j - ads ? j = 1 to 7300 ads dsnu register dark dc level v out v out f tg light v out on off v 1
m pd3728 16 data sheet s13878ej1v0ds00 9. register imbalance: ri the rate of the difference between the averages of the output voltage of odd and even pixels, against the average output voltage of all the valid pixels. n : number of valid pixels v j : output voltage of each pixel 10. random noise: s random noise s is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). v i : a valid pixel output signal among all of the valid pixels for each color this is measured by the dc level sampling of only the signal level, not by cds (correlated double sampling). ri (%) = 2 n j = 1 n 2 (v 2j ?1 v 2j ) 1 n j = 1 n v j 100 ? ? s (mv) = , v = s i=1 100 (v i ?v) 2 s i=1 100 v i 100 100 1 v 1 v 100 v 2 ? ? line 2 line 100 line 1 v out
m pd3728 17 data sheet s13878ej1v0ds00 standard characteristic curves (nominal) dark output temperature characteristic storage time output voltage characteristic (t a = +25 c) operating ambient temperature t a ( c) storage time (ms) 8 4 2 1 0.5 0.25 0.1 10 0 20304050 relative output voltage relative output voltage 2 1 0.2 0.1 1510 100 b b g g r 80 60 40 20 0 400 500 600 700 800 wavelength (nm) response ratio (%) total spectral response characteristics (without infrared cut filter) (t a = +25 c)
m pd3728 18 data sheet s13878ej1v0ds00 application circuit example remarks 1. pin 9 ( f 10) and pin 28 ( f 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 mhz or so. 2. the inverters shown in the above application circuit example are the 74ac04. v out 3 gnd v out 4 v out 1 v out 6 v out 2 v out 5 gnd gnd gnd gnd v od rb nc gnd clb nc nc nc nc 2 nc 1 2 gnd nc nc 1 tg1 nc nc tg2 tg3 10 20 1l pd3728 + 10 f/16 v 0.1 f + 47 f/25 v 0.1 f +5 v +12 v + 10 f/16 v 0.1 f +5 v b4 b6 b5 b1 b3 b2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 2 w 2 w 2 w 2 w 2 w 2 w 2 w 2 w 47 w 47 w 47 w 2 w 10 w 1 tg clb rb 2 mm m m mm m f f f f f f f f f f f f ff f ff
m pd3728 19 data sheet s13878ej1v0ds00 +12 v 110 w 4.7 k w 47 f/25 v 2sa1005 2sc945 1 k w 47 w + 0.1 f ccd v out b1 to b6 equivalent circuit m m
m pd3728 20 data sheet s13878ej1v0ds00 package drawing name dimensions refractive index glass cap 93.0 13.6 1.0 1.5 1 the 1st valid pixel the center of the pin1 2 the 1st valid pixel the center of the package (reference) 3 the surface of the chip the top of the glass cap (reference) 4 the bottom of the package the surface of the chip 36d-1ccd-pkg1-1 ccd linear image sensor 36-pin ceramic dip (600mil) 2.54 20.32 15.24 94.00 0.50 0.46 0.05 1.27 0.05 (4.33) 3.50 0.5 2.0 0.3 4 0.25 0.05 0.97 0.3 3.30 0.35 88.9 0.6 14.99 0.3 9.5 0.9 1 (35.0) 2 (2.33) 3 (unit : mm) the 1st valid pixel
m pd3728 21 data sheet s13878ej1v0ds00 notes on the use of the package the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. when mounting the package, use a circuit board which will not subject the package to bending stress, or use a socket. for this product, the reference value for the three-point bending strength note is 30 kg. avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). note three-point bending strength test distance between supports: 70 mm, support r: r 2 mm, loading rate: 0.5 mm / min. load load 70 mm 70 mm
m pd3728 22 data sheet s13878ej1v0ds00 [memo]
m pd3728 23 data sheet s13878ej1v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd3728 [memo] the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8

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